• Journal of Internet Computing and Services
    ISSN 2287 - 1136 (Online) / ISSN 1598 - 0170 (Print)
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Implementation algorithm and system for generating PWM frequency for berthing the train at station


Eun-Taek Han, Chang-Sik Park, Ik-Jae Kim, Dong-Kyoo Shin, Journal of Internet Computing and Services, Vol. 24, No. 5, pp. 37-50, Oct. 2023
10.7472/jksii.2023.24.5.37, Full Text:  HTML
Keywords: Phase locked loop, Direct Digital Synthesizer, Hard ware Description Language, Reliability, Availability

Abstract

In general, PLL or DDS are mainly used as precise and stable frequency synthesis methods. For stable operation, a PWM frequency generation algorithm was designed and implemented using FPGA. This is an algorithm that creates a frequency 8,192 times the target frequency and then performs the D flip-flop 13 times to generate multiple frequencies with a precision of 1 Hz. Using the designed algorithm, it is applied to the Berthing system for stopping trains in station. The applied product was developed and tested against the existing operating system to confirm its superior performance in terms of frequency generation accuracy.


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Cite this article
[APA Style]
Han, E., Park, C., Kim, I., & Shin, D. (2023). Implementation algorithm and system for generating PWM frequency for berthing the train at station. Journal of Internet Computing and Services, 24(5), 37-50. DOI: 10.7472/jksii.2023.24.5.37.

[IEEE Style]
E. Han, C. Park, I. Kim, D. Shin, "Implementation algorithm and system for generating PWM frequency for berthing the train at station," Journal of Internet Computing and Services, vol. 24, no. 5, pp. 37-50, 2023. DOI: 10.7472/jksii.2023.24.5.37.

[ACM Style]
Eun-Taek Han, Chang-Sik Park, Ik-Jae Kim, and Dong-Kyoo Shin. 2023. Implementation algorithm and system for generating PWM frequency for berthing the train at station. Journal of Internet Computing and Services, 24, 5, (2023), 37-50. DOI: 10.7472/jksii.2023.24.5.37.