An Optimum Architecture for Implementing SEED Cipher Algorithm with Efficiency

Shin Kwang-Cheul; Lee Haeng-Woo

An Optimum Architecture for Implementing SEED Cipher Algorithm with Efficiency

Shin Kwang-Cheul, Lee Haeng-Woo, Journal of Internet Computing and Services, Vol. 7, No. 1, pp. 49-58, Feb. 2006
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Keywords: SEED, hardware circuit design, pipelined systolic array

Abstract

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 12B-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array, This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We have designed the circuit with the VHDL coding, implemented with a FPGA of 50,000 gates.

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Cite this article

[APA Style]

Kwang-Cheul, S. & Haeng-Woo, L. (2006). An Optimum Architecture for Implementing SEED Cipher Algorithm with Efficiency. Journal of Internet Computing and Services, 7(1), 49-58.

[IEEE Style]

S. Kwang-Cheul and L. Haeng-Woo, "An Optimum Architecture for Implementing SEED Cipher Algorithm with Efficiency," Journal of Internet Computing and Services, vol. 7, no. 1, pp. 49-58, 2006.

[ACM Style]

Shin Kwang-Cheul and Lee Haeng-Woo. 2006. An Optimum Architecture for Implementing SEED Cipher Algorithm with Efficiency. Journal of Internet Computing and Services, 7, 1, (2006), 49-58.