Modeling of Input Buffered Multistage Interconnection Networks using Small Clock Cycle Scheme

Mun Youngsong

Modeling of Input Buffered Multistage Interconnection Networks using Small Clock Cycle Scheme

Mun Youngsong, Journal of Internet Computing and Services, Vol. 5, No. 3, pp. 35-44, Jun. 2004
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Abstract

In packet switching using multistage interconnection networks (MIN's), it is generally assumed that the packet movements successively propagate from the last stage to the first stage in one network cycle. However, Ding and Bhuyan has shown that the network performance can be significantly improved if the packet movements are confined within each pair of adjacent stages using small clock cycles. In this paper, an analytical model for evaluating the performance of input-buffered MlN's employing this network cycle approach is proposed, The effectiveness of the proposed model is confirmed by comparing results from the simulation as well as from Ding and Bhuyan model.

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Cite this article

[APA Style]

Youngsong, M. (2004). Modeling of Input Buffered Multistage Interconnection Networks using Small Clock Cycle Scheme. Journal of Internet Computing and Services, 5(3), 35-44.

[IEEE Style]

M. Youngsong, "Modeling of Input Buffered Multistage Interconnection Networks using Small Clock Cycle Scheme," Journal of Internet Computing and Services, vol. 5, no. 3, pp. 35-44, 2004.

[ACM Style]

Mun Youngsong. 2004. Modeling of Input Buffered Multistage Interconnection Networks using Small Clock Cycle Scheme. Journal of Internet Computing and Services, 5, 3, (2004), 35-44.